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freescale semiconductor data sheet document number: MSC7113 rev. 11, 4/2008 ? freescale semiconductor, inc., 2004, 2008. all rights reserved. MSC7113 map-bga?400 17 mm 17 mm ?starcore ? sc1400 dsp extended core with one sc1400 dsp core, 192 kbyte of internal sram m1 memory, 16 way 16 kbyte instruction cache (icache), four-entry write buffer, programmable interrupt controller (pic), and low-power wait and stop processing modes. ? 8 kbyte boot rom. ? ahb-lite crossbar switch that allows parallel data transfers between four master ports and six slave ports, where each port connects to an ahb-lite bus; fixed or round robin priority programmable at each slave port; programmable bus parking at each slave port; low power mode. ? internal pll generates up to 266 mhz clock for the sc1400 core and up to 133 mhz for the crossbar switch, dma channels, m2 memory, and other peripherals. ? clock synthesis module provides predivision of pll input clock; independent clocking of the internal timers and ddr module; programmable operation in the sc1400 low power stop mode; independent shutdown of different regions of the device. ? enhanced 16-bit wide host interface (hdi16) provides a glueless connection to industry-standard microcomputers, microprocessors, and dsps and can also operate with an 8-bit host data bus, making if fully compatible with the dsp56300 hi08 from the external host side. ? ddr memory controller that supports byte enables for up to a 32-bit data bus; glueless interface to 133 mhz 14-bit page mode ddr-ram; 14-bit external address bus supporting up to 1 gbyte; and 16-bit or 32-bit external data bus. ? programmable memory interface with independent read buffers, programmable predictive read feature for each buffer, and a write buffer. ? system control unit performs software watchdog timer function; includes programmable bus time-out monitors on ahb-lite slave buses; includes bus error detection and programmable time-out monitors on ahb-lite master buses; and has address out-of-range detection on each crossbar switch buses. ? event port collects and counts important signal events including dma and interrupt requests and trigger events such as interrupts, breakpoints, dma transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the oce10. ? multi-channel dma controller with 32 time-multiplexed unidirectional channels, priority-based time-multiplexing between channels using 32 internal priority levels, fixed- or round-robin-priority operation, major-minor loop structure, and done or drack protocol from requesting units. ? two independent tdm modules with independent receive and transmit, programmable sharing of frame sync and clock, programmable word size (8 or 16-bit), hardware-base a-law/ -law conversion, up to 50 mbps data rate per tdm, up to 128 channels, with glueless interface to e1/t1 frames and mvip, scas, and h.110 buses. ? ethernet controller with support for 10/100 mbps mii/rmii designed to comply with ieee std. 802.3?, 802.3u?, 802.3x?, and 802.3ac?; with internal receive and transmit fifos and a fifo controller; direct access to internal memories via its own dma controller; full and half duplex operation; programmable maximum frame length; virtual local area network (vlan) tag and priority support; retransmission of transmit fifo following collision; crc generation and verification for inbound and outbound packets; and address recognition including promiscuous, broadcast, individual address. hash/exact match, and multicast hash match. ? uart with full-duplex operation up to 5.0 mbps. ? up to 41 general-purpose input/output (gpio) ports. ?i 2 c interface that allows booting from eeprom devices up to 1 mbyte. ? two quad timer modules, each with sixteen configurable 16-bit timers. ? fieldbist? unit detects and provides visibility into unlikely field failures for systems with high availability to ensure structural integrity, that the device operates at the rated speed, is free from reliability defects, and reports diagnostics for partial or complete device inoperability. ? standard jtag interface allows easy integration to system firmware and internal on-chip emulation (oce10) module. ? optional booting external host via 8-bit or 16-bit access through the hdi16, i 2 c, or spi using in the boot rom to access serial spi flash/eeprom devices; different clocking options during boot with the pll on or off using a variety of input frequency ranges. low-cost 16-bit dsp with ddr controller and 10/100 mbps ethernet mac
MSC7113 data sheet, rev. 11 freescale semiconductor 2 table of contents 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 map-bga ball layout diagrams . . . . . . . . . . . . . . . . . .4 1.2 signal list by ball location. . . . . . . . . . . . . . . . . . . . . . .6 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2 recommended operating conditions. . . . . . . . . . . . . .18 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .18 2.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . .19 2.5 ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3 hardware design considerations . . . . . . . . . . . . . . . . . . . . . .41 3.1 thermal design considerations . . . . . . . . . . . . . . . . . .41 3.2 power supply design considerations. . . . . . . . . . . . . .42 3.3 estimated power usage calculations. . . . . . . . . . . . . .49 3.4 reset and boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.5 ddr memory system guidelines . . . . . . . . . . . . . . . . .53 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 list of figures figure 1. MSC7113 block diagram. . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. MSC7113 molded array process-ball grid array (map-bga), top view . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. MSC7113 molded array process-ball grid array (map-bga), bottom view . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. timing diagram for a reset configuration write . . . . 24 figure 5. ddr dram input timing diagram . . . . . . . . . . . . . . 24 figure 6. ddr dram output timing diagram . . . . . . . . . . . . . 26 figure 7. ddr dram ac test load. . . . . . . . . . . . . . . . . . . . . 26 figure 8. tdm receive signals. . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. tdm transmit signals . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. ethernet receive signal timing . . . . . . . . . . . . . . . . . 28 figure 11. ethernet receive signal timing . . . . . . . . . . . . . . . . . 29 figure 12. asynchronous input signal timing . . . . . . . . . . . . . . . 29 figure 13. serial management channel timing . . . . . . . . . . . . . 30 figure 14. read timing diagram, single data strobe . . . . . . . . 32 figure 15. read timing diagram, double data strobe . . . . . . . . 33 figure 16. write timing diagram, single data strobe. . . . . . . . . 33 figure 17. write timing diagram, double data strobe . . . . . . . . 34 figure 18. host dma read timing diagram, hpcr[oad] = 0 . . 34 figure 19. host dma write timing diagram, hpcr[oad] = 0 . . 35 figure 20. i2c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. uart input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22. uart output timing . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23. ee pin timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 24. evnt pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 25. gpi/gpo pin timing . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26. test clock input timing diagram . . . . . . . . . . . . . . . . 39 figure 27. boundary scan (jtag) timing diagram . . . . . . . . . . 40 figure 28. test access port timing diagram . . . . . . . . . . . . . . . 40 figure 29. trst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 30. voltage sequencing case 1 . . . . . . . . . . . . . . . . . . . . 43 figure 31. voltage sequencing case 2 . . . . . . . . . . . . . . . . . . . . 44 figure 32. voltage sequencing case 3 . . . . . . . . . . . . . . . . . . . . 45 figure 33. voltage sequencing case 4 . . . . . . . . . . . . . . . . . . . . 46 figure 34. voltage sequencing case 5 . . . . . . . . . . . . . . . . . . . . 47 figure 35. pll power supply filter circuits . . . . . . . . . . . . . . . . 48 figure 36. sstl termination techniques . . . . . . . . . . . . . . . . . . 53 figure 37. sstl power value . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
MSC7113 data sheet, rev. 11 freescale semiconductor 3 figure 1. MSC7113 block diagram mux boot rom (8 kb) rs-232 apb apb bridge 64 uart external memory interrupts interrupt control hdi16 32 host interface (hdi16) external bus timers 2 tdms dsp extended note: the arrows show the interface port 32 128 32 sc1400 core cache instruction (16 kb) extended core interface unit fetch m1 sram (192 kb) 64 64 128 64 ahb-lite crossbar switch tdm pxaxb 128 64 64 pll/clock pll/clock oce10 trace buffer (8 kb) to/from oce10 ib bridge 32 events 32 ipbus to dma to emi core amic amec asm1 asm2 asemi asth asapb from ipbus i 2 c i 2 c watchdog event port btms asib gpio gpio ethernet mac ament 64 mii/rmii direction of the transfer. dma (32 channel) 64 jtag jtag port amdma to ipbus system ctrl
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 4 1 pin assignments this section includes diagrams of the MSC7113 package ball grid array layouts and pinout allocation tables. 1.1 map-bga ball layout diagrams top and bottom views of the map-bga package are shown in figure 2 and figure 3 with their ball location index numbers. figure 2. MSC7113 molded array process-ball grid array (map-bga), top view 1234567891011121314151617181920 a gnd gnd dqm1 dqs2 ck ck hd15 hd12 hd10 hd7 hd6 hd4 hd1 hd0 gnd nc nc nc nc nc b v ddm nc cs0 dqm2 dqs3 dqs0 cke we hd14 hd11 hd8 hd5 hd2 nc nc nc nc nc nc nc c d24 d30 d25 cs1 dqm3 dqm0 dqs1 ras cas hd13hd9hd3ncncncncncncncnc d v ddm d28 d27 gnd v ddm v ddm v ddm v ddm v ddm v ddm v ddio v ddio v ddio v ddio v ddio v ddio v ddc nc nc nc e gnd d26 d31 v ddm v ddm v ddc v ddc v ddc v ddc v ddm v ddio v ddio v ddio v ddio v ddio v ddc v ddc nc nc nc f v ddm d15 d29 v ddc v ddc v ddc gnd gnd gnd v ddm v ddm gnd gnd gnd v ddio v ddc v ddc nc nc nc g gnd d13 gnd v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddio v ddc nc nc nc hd14d12d11 v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddio v ddc nc ha2 ha1 jd10 v ddm d9 v ddm v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddc ha3 hack hreq k d0 gnd d8 v ddc v ddm gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddio v ddc ha0 hdds hds l d1 gnd d3 v ddc v ddm gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddio v ddio v ddc hcs2 hcs1 hrw md2 v ddm d5 v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddc v ddc sda utxd urxd nd4d6 v ref v ddm v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddc v ddc clkin scl v sspll pd7d17d16 v ddm v ddm v ddm gnd gnd gnd gnd gnd gnd gnd gnd v ddio v ddio v ddc poreset tpsel v ddpll r gnd d19 d18 v ddm v ddm v ddm gnd v ddm gnd v ddm gnd gnd v ddio gnd v ddio v ddio v ddc tdo ee0 test0 t v ddm d20 d22 v ddm v ddm v ddc v ddm v ddm v ddc v ddm v ddm v ddio v ddio v ddio v ddio v ddc v ddc mdio tms hreset u gnd d21 d23 v ddm v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc v ddc col tck trst v v ddm nc a13 a11 a10 a5 a2 ba0 nc evnt0 evnt4 t0tck t1rfs t1td tx_er rxd2 rxd0 tx_en crs tdi wgnd v ddm a12 a8 a7 a6 a3 nc evnt1 evnt2 t0rfs t0tfs t1rd t1tfs txd2 rxd3 txd1 txclk rx_er mdc y v ddm gnda9a1a0a4ba1nmi evnt3 t0rck t0rd totd t1rck t1tck txd3 rxclk txd0 rxd1 gnd rx_dv top view
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 5 figure 3. MSC7113 molded array process-ball grid array (map-bga), bottom view 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a nc nc nc nc nc gnd hd0 hd1 hd4 hd6 hd7 hd10 hd12 hd15 ck ck dqs2 dqm1 gnd gnd b nc nc nc nc nc nc nc hd2 hd5 hd8 hd11 hd14 we cke dqs0 dqs3 dqm2 cs0 nc v ddm c ncncncncncncncnchd3hd9hd13cas ras dqs1 dqm0 dqm3 cs1 d25 d30 d24 d ncncnc v dd v ddio v ddio v ddio v ddio v ddio v ddio v ddm v ddm v ddm v ddm v ddm v ddm gnd d27 d28 v ddm e ncncnc v dd v dd v ddio v ddio v ddio v ddio v ddio v ddm v dd v dd v dd v dd v ddm v ddm d31 d26 gnd f ncncnc v dd v dd v ddio gnd gnd gnd v ddm v ddm gnd gnd gnd v dd v dd v dd d29 d15 v ddm g ncncnc v dd v ddio v ddio gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm gnd d13 gnd hha1ha2nc v dd v ddio v ddio gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm d11 d12 d14 j hreq hack ha3 v dd v ddio gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm v ddm d9 v ddm d10 khds hdds ha0 v dd v ddio v ddio gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddm v dd d8 gnd d0 l hrw hcs1 hcs2 v dd v ddio v ddio v ddio gnd gnd gnd gnd gnd gnd gnd gnd v ddm v dd d3 gnd d1 murxdutxdsda v dd v dd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm d5 v ddm d2 n v sspll scl clkin v dd v dd v ddio gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm v ddm v ref d6 d4 p v ddpll tpsel poreset v dd v ddio v ddio gnd gnd gnd gnd gnd gnd gnd gnd v ddm v ddm v ddm d16 d17 d7 r test0 ee0 tdo v dd v ddio v ddio gnd v ddio gnd gnd v ddm gnd v ddm gnd v ddm v ddm v ddm d18 d19 gnd t hreset tms mdio v dd v dd v ddio v ddio v ddio v ddio v ddm v ddm v dd v ddm v ddm v dd v ddm v ddm d22 d20 v ddm utrst tck col v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ddm d23 d21 gnd v tdi crs tx_en rxd0 rxd2 tx_er t1td t1rfs t0tck evnt4 evnt0 nc ba0 a2 a5 a10 a11 a13 nc v ddm w mdc rx_er txclk txd1 rxd3 txd2 t1tfs t1rd t0tfs t0rfs evnt2 evnt1 nc a3 a6 a7 a8 a12 v ddm gnd y rx_dv gnd rxd1 txd0 rxclk txd3 t1tck t1rck totd t0rd t0rck evnt3 nmi ba1a4a0a1a9gnd v ddm bottom view
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 6 1.2 signal list by ball location table 1 lists the signals sorted by ball number and configuration. table 1. MSC7113 signals by ball designator number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate a1 gnd a2 gnd a3 dqm1 a4 dqs2 a5 ck a6 ck a7 gpic7 gpoc7 hd15 a8 gpic4 gpoc4 hd12 a9 gpic2 gpoc2 hd10 a10 reserved hd7 a11 reserved hd6 a12 reserved hd4 a13 reserved hd1 a14 reserved hd0 a15 gnd a16 (1l44x) nc a16 (1m88b) bm3 gpid8 gpod7 reserved a17 nc a18 nc a19 nc a20 nc b1 v ddm b2 nc b3 cs0 b4 dqm2 b5 dqs3 b6 dqs0 b7 cke b8 we b9 gpic6 gpoc6 hd14 b10 gpic3 gpoc3 hd11 b11 gpic0 gpoc0 hd8 b12 reserved hd5 b13 reserved hd2 b14 nc
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 7 b15 (1l44x) nc b15 (1m88b) bm2 gpid7 gpod7 reserved b16 nc b17 nc b18 nc b19 nc b20 nc c1 d24 c2 d30 c3 d25 c4 cs1 c5 dqm3 c6 dqm0 c7 dqs1 c8 ras c9 cas c10 gpic5 gpoc5 hd13 c11 gpic1 gpoc1 hd9 c12 reserved hd3 c13 nc c14 nc c15 nc c16 nc c17 nc c18 nc c19 nc c20 nc d1 v ddm d2 d28 d3 d27 d4 gnd d5 v ddm d6 v ddm d7 v ddm d8 v ddm d9 v ddm d10 v ddm d11 v ddio table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 8 d12 v ddio d13 v ddio d14 v ddio d15 v ddio d16 v ddio d17 v ddc d18 nc d19 nc d20 nc e1 gnd e2 d26 e3 d31 e4 v ddm e5 v ddm e6 v ddc e7 v ddc e8 v ddc e9 v ddc e10 v ddm e11 v ddio e12 v ddio e13 v ddio e14 v ddio e15 v ddio e16 v ddc e17 v ddc e18 nc e19 nc e20 nc f1 v ddm f2 d15 f3 d29 f4 v ddc f5 v ddc f6 v ddc f7 gnd f8 gnd f9 gnd table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 9 f10 v ddm f11 v ddm f12 gnd f13 gnd f14 gnd f15 v ddio f16 v ddc f17 v ddc f18 nc f19 nc f20 nc g1 gnd g2 d13 g3 gnd g4 v ddm g5 v ddm g6 gnd g7 gnd g8 gnd g9 gnd g10 gnd g11 gnd g12 gnd g13 gnd g14 gnd g15 v ddio g16 v ddio g17 v ddc g18 nc g19 nc g20 nc h1 d14 h2 d12 h3 d11 h4 v ddm h5 v ddm h6 gnd h7 gnd table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 10 h8 gnd h9 gnd h10 gnd h11 gnd h12 gnd h13 gnd h14 gnd h15 v ddio h16 v ddio h17 v ddc h18 nc h19 reserved ha2 h20 reserved ha1 j1 d10 j2 v ddm j3 d9 j4 v ddm j5 v ddm j6 v ddm j7 gnd j8 gnd j9 gnd j10 gnd j11 gnd j12 gnd j13 gnd j14 gnd j15 gnd j16 v ddio j17 v ddc j18 (1l44x) reserved ha3 j18 (1m88b) gpic11 gpoc11 ha3 j19 reserved hack /hack or hrrq /hrrq j20 hdsp reserved hreq /hreq or htrq /htrq k1 d0 k2 gnd k3 d8 k4 v ddc table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 11 k5 v ddm k6 gnd k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 v ddio k16 v ddio k17 v ddc k18 reserved ha0 k19 reserved hdds k20 reserved hds /hds or hwr /hwr l1 d1 l2 gnd l3 d3 l4 v ddc l5 v ddm l6 gnd l7 gnd l8 gnd l9 gnd l10 gnd l11 gnd l12 gnd l13 gnd l14 v ddio l15 v ddio l16 v ddio l17 v ddc l18 (1l44x) reserved hcs2 /hcs2 l18 (1m88b) gpib11 gpob11 hcs2 /hcs2 l19 reserved hcs1 /hcs1 l20 reserved hrw or hrd /hrd m1 d2 table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 12 m2 v ddm m3 d5 m4 v ddm m5 v ddm m6 gnd m7 gnd m8 gnd m9 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 v ddc m17 v ddc m18 gpia14 irq15 gpoa14 sda m19 gpia12 irq3 gpoa12 utxd m20 gpia13 irq2 gpoa13 urxd n1 d4 n2 d6 n3 v ref n4 v ddm n5 v ddm n6 v ddm n7 gnd n8 gnd n9 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 v ddio n16 v ddc n17 v ddc n18 clkin n19 gpia15 irq14 gpoa15 scl table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 13 n20 v sspll p1 d7 p2 d17 p3 d16 p4 v ddm p5 v ddm p6 v ddm p7 gnd p8 gnd p9 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 v ddio p16 v ddio p17 v ddc p18 poreset p19 tpsel p20 v ddpll r1 gnd r2 d19 r3 d18 r4 v ddm r5 v ddm r6 v ddm r7 gnd r8 v ddm r9 gnd r10 v ddm r11 gnd r12 gnd r13 v ddio r14 gnd r15 v ddio r16 v ddio r17 v ddc table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 14 r18 tdo r19 reserved ee0/dbreq r20 test0 t1 v ddm t2 d20 t3 d22 t4 v ddm t5 v ddm t6 v ddc t7 v ddm t8 v ddm t9 v ddc t10 v ddm t11 v ddm t12 v ddio t13 v ddio t14 v ddio t15 v ddio t16 v ddc t17 v ddc t18 reserved mdio t19 tms t20 hreset u1 gnd u2 d21 u3 d23 u4 v ddm u5 v ddc u6 v ddc u7 v ddc u8 v ddc u9 v ddc u10 v ddc u11 v ddc u12 v ddc u13 v ddc u14 v ddc u15 v ddc table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
pin assignments MSC7113 data sheet, rev. 11 freescale semiconductor 15 u16 v ddc u17 v ddc u18 reserved col u19 tck u20 trst v1 v ddm v2 nc v3 a13 v4 a11 v5 a10 v6 a5 v7 a2 v8 ba0 v9 nc v10 reserved evnt0 v11 swte gpia16 irq12 gpoa16 evnt4 v12 gpia8 irq6 gpoa8 t0tck v13 gpia4 irq1 gpoa4 t1rfs v14 gpia0 irq11 gpoa0 t1td v15 gpia28 irq17 gpoa28 tx_er reserved v16 gpid6 gpod6 rxd2 reserved v17 gpia22 irq22 gpoa22 rxd0 v18 gpia24 irq24 gpoa24 tx_en v19 reserved crs v20 tdi w1 gnd w2 v ddm w3 a12 w4 a8 w5 a7 w6 a6 w7 a3 w8 nc w9 gpia17 irq13 gpoa17 evnt1 clko w10 bm0 gpic14 gpoc14 evnt2 w11 gpia10 irq5 gpoa10 t0rfs w12 gpia7 irq7 gpoa7 t0tfs w13 gpia3 irq8 gpoa3 t1rd table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
MSC7113 data sheet, rev. 11 pin assignments freescale semiconductor 16 w14 gpia1 irq10 gpoa1 t1tfs w15 gpid4 gpod4 txd2 reserved w16 gpia27 irq18 gpoa27 rxd3 reserved w17 gpia19 irq19 gpoa19 txd1 w18 gpia23 irq23 gpoa23 txclk or refclk w19 gpia26 irq26 gpoa26 rx_er w20 h8bit reserved mdc y1 v ddm y2 gnd y3 a9 y4 a1 y5 a0 y6 a4 y7 ba1 y8 reserved nmi reserved y9 bm1 gpic15 gpoc15 evnt3 y10 gpia11 irq4 gpoa11 t0rck y11 gpia9 gpoa9 t0rd y12 gpia6 gpoa6 t0td y13 gpia5 irq0 gpoa5 t1rck y14 gpia2 irq9 gpoa2 t1tck y15 gpia29 irq16 gpia29 txd3 reserved y16 gpid5 gpod5 rxclk reserved y17 gpia20 irq20 gpoa20 txd0 y18 gpia21 irq21 gpoa21 rxd1 y19 gnd y20 gpia25 irq25 gpoa25 rx_dv or crs_dv table 1. MSC7113 signals by ball designator (continued) number signal names end of reset software controlled hardware controlled gpi enabled (default) interrupt enabled gpo enabled primary alternate
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 17 2 electrical characteristics this document contains detailed information on power co nsiderations, dc/ac electrical characteristics, and ac timing specifications. for addition al information, see the msc711x reference manual . 2.1 maximum ratings in calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is cal culated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using th e worst case for the same parameters in the opposite directio n. therefore, a ?maximum? value for a speci fication never occurs in the same devi ce with a ?minimum? value for another specification; adding a maximu m to a minimum represents a condition that can never exist. table 2 describes the maximum electri cal ratings for the MSC7113. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ). table 2. absolute maximum ratings rating symbol value unit core supply voltage v ddc 1.5 v memory supply voltage v ddm 4.0 v pll supply voltage v ddpll 1.5 v i/o supply voltage v ddio ?0.2 to 4.0 v input voltage v in (gnd ? 0.2) to 4.0 v reference voltage v ref 4.0 v maximum operating temperature t j 105 c minimum operating temperature t a ?40 c storage temperature range t stg ?55 to +150 c notes: 1. functional operating conditions are given in table 3. 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the listed limits may affect device reliability or cause permanent damage. 3. section 3.1 , thermal design considerations includes a formula for computing the chip junction temperature (t j ).
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 18 2.2 recommended operating conditions table 3 lists recommended operating conditions. proper device operation outside of these conditions is not guaranteed. 2.3 thermal characteristics table 4 describes thermal characteristics of the MSC7113 for the map-bga package. section 3.1 , thermal design considerations explains these characteristics in detail. table 3. recommended operating conditions rating symbol value unit core supply voltage v ddc 1.14 to 1.26 v memory supply voltage v ddm 2.38 to 2.63 v pll supply voltage v ddpll 1.14 to 1.26 v i/o supply voltage v ddio 3.14 to 3.47 v reference voltage v ref 1.19 to 1.31 v operating temperature range t j t a maximum: 105 minimum: ?40 c c table 4. thermal characteristics for map-bga package characteristic symbol map-bga 17 17 mm 5 unit natural convection 200 ft/min (1 m/s) airflow junction-to-ambient 1, 2 r ja 39 31 c/w junction-to-ambient, four-layer board 1, 3 r ja 23 20 c/w junction-to-board 4 r jb 12 c/w junction-to-case 5 r jc 7 c/w junction-to-package-top 6 jt 2 c/w notes: 1. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power di ssipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 wit h the board horizontal. 4. thermal resistance between the die and the printed circuit boar d per jedec jesd 51-8. boar d temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per jedec jesd51-2.
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 19 2.4 dc electrical characteristics this section describes the dc electrical characteristics for the MSC7113. note: the leakage current is measured for nom inal voltage values must vary in th e same direction (for example, both v ddio and v ddc vary by +2 percent or both vary by ?2 percent). ta b l e 6 lists the ddr dram capacitance. table 5. dc electrical characteristics characteristic symbol min typical max unit core and pll voltage v ddc v ddpll 1.14 1.2 1.26 v dram interface i/o voltage 1 v ddm 2.375 2.5 2.625 v i/o voltage v ddio 3.135 3.3 3.465 v dram interface i/o reference voltage 2 v ref 0.49 v ddm 1.25 0.51 v ddm v dram interface i/o termination voltage 3 vtt v ref ? 0.04 v ref v ref + 0.04 v input high clkin voltage v ihclk 2.4 3.0 3.465 v dram interface input high i/o voltage v ihm v ref + 0.28 v ddm v ddm + 0.3 v dram interface input low i/o voltage v ilm ?0.3 gnd v ref ? 0.18 v input leakage current, v in = v ddio i in ?1.0 0.09 1 a v ref input leakage current i vref ?? 5a tri-state (high impedance off state) leakage current, v in = v ddio i oz ?1.0 0.09 1 a signal low input current, v il = 0.4 v i l ?1.0 0.09 1 a signal high input current, v ih = 2.0 v i h ?1.0 0.09 1 a output high voltage, i oh = ?2 ma, except open drain pins v oh 2.0 3.0 ? v output low voltage, i ol = 5 ma v ol ?00.4v typical power at 266 mhz 5 p ? 293.0 ? mw notes: 1. the value of v ddm at the MSC7113 device must remain within 50 mv of v ddm at the dram device at all times. 2. v ref must be equal to 50% of v ddm and track v ddm variations as measured at the re ceiver. peak-to-peak noise must not exceed 2% of the dc value. 3. v tt is not applied directly to the MSC7113 device. it is the le vel measured at the far end signal termination. it should be equal to v ref . this rail should track variations in the dc level of v ref . 4. output leakage for the memory interface is measured with all outputs disabled, 0 v v out v ddm . 5. the core power values were measured.using a standard efr pat tern at typical conditions (25c, 300 mhz, 1.2 v core). table 6. ddr dram capacitance parameter/condition symbol max unit input/output capacitance: dq, dqs c io 30 pf delta input/output capacitance: dq, dqs c dio 30 pf note: these values were measured under the following conditions: ? v ddm = 2.5 v 0.125 v ? f = 1 mhz ? t a = 25 c ? v out = v ddm /2 ? v out (peak to peak) = 0.2 v
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 20 2.5 ac timings this section presents timing diagrams and specifications for individual signals and parallel i/o outputs and inputs. all ac timings are based on a 30 pf load, ex cept where noted otherwise, and a 50 transmission line. for any additional pf, use the following equations to compute the delay: ? standard interface: 2.45 + (0.054 c load ) ns ? ddr interface: 1.6 + (0.002 c load ) ns 2.5.1 clock and timing signals the following tables describe clock signal characteristics. table 6 shows the maximum frequency values for internal (core, reference, and peripherals) and external ( clko ) clocks. you must ensure that maximu m frequency values are not exceeded (see for the allowable ranges when using the pll). 2.5.2 configuring clock frequencies this section describes important requirements for configurin g clock frequencies in the MSC7113 device when using the pll block. to configure the device clocking, you must progra m four fields in the clock control register (clkctl): ? plldvf field. specifies the pl l division factor. the output of the divider block is the input to the multiplier block. ? pllmltf field. specifies the pll multiplication factor. the output from the multiplier block is the vco . ? rng field. selects the av ailable pll frequency range. ? cksel field. selects the source for the core clock. there are restrictions on the frequency range permitted at the beginning of the multiplication portion of the pll that affect t he allowable values for the plldvf and pllmlt f fields. the following sections define these restrictions and provide guidelines to configure the device clocking when using the pll. re fer to the clock and power management chapter in the msc711x reference manual for details on the clock programming model. table 6. maximum frequencies characteristic maximum in mhz mask set 1l44x mask set 1m88b core clock frequency (clock) 200 266 external output clock frequency (clko) 50 67 memory clock frequency (ck, ck ) 100 133 tdm clock frequency (txrck, txtck) 50 67 table 7. clock frequencies in mhz characteristic symbol min max mask set 1l44x mask set 1m88b clkin frequency f clkin 10 100 100 clock frequency f core ? 200 266 ck, ck frequency f ck ? 100 133 tdmxrck, tdmxtck frequency f tdmck ?50 50 clko frequency f cko ?50 67 ahb/ipbus/apb clock frequency f bck ? 100 133 note: the rise and fall time of external clocks should be 5 ns maximum table 8. system clock parameters characteristic min max unit clkin frequency 10 100 mhz clkin slope ?5ns clkin frequency jitter (peak-to-peak) ? 1000 ps clko frequency jitter (peak-to-peak) ? 150 ps
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 21 2.5.2.1 pll multiplier restrictions there are two restrictions for correct usage of the pll block: ? the input frequency to the pll multiplier block (that is, the output of the divider) must be in the range 10.5?19.5 mhz. ? the output frequency of the pll multiplier must be in the range 300-600 mhz. when programming the pll for a desired output frequency us ing the plldvf, pllmltf, and rng fields, you must meet these constraints. 2.5.2.2 division factors and corresponding clkin frequency range the value of the plldvf field determines the allowable clkin frequency range, as shown in table 9 . 2.5.2.3 multiplication factor range the multiplier block output frequency ranges depend on the divided input clock frequency as shown in table 10 . 2.5.2.4 allowed core clock frequency range the frequency delivered to the core, extended core, and peripherals depends on the value of the clkctrl[rng] bit as shown in table 11 . this bit along with the cksel determines the frequency range of the core clock. table 9. clkin frequency ranges by divide factor value plldvf field value divide factor clkin frequency range comments 0x00 1 10.5 to 19.5 mhz pre-division by 1 0x01 2 21 to 39 mhz pre-division by 2 0x02 3 31.5 to 58.5 mhz pre-division by 3 0x03 4 42 to 78 mhz pre-division by 4 0x04 5 52.5 to 97.5 mhz pre-division by 5 0x05 6 63 to 100 mhz pre-division by 6 0x06 7 73.5 to 100 mhz pre-division by 7 0x07 8 84 to 100 mhz pre-division by 8 0x08 9 94.5 to 100 mhz pre-division by 9 note: the maximum clkin frequency is 100 mhz. therefore, the plldvf value must be in the range from 1?9. table 10. pllmltf ranges multiplier block (loop) output range minimum pllmltf value maximum pllmltf value 266 [divided input clock (pllmltf + 1)] 532 mhz 266/divided input clock 532/divided input clock note: this table results from the allowed range for f loop . the minimum and maximum multiplication factors are dependent on the frequency of the divided input clock. table 11. f vco frequency ranges clkctrl[rng] value allowed range of f vco 1 266 f vco 532 mhz 0 133 f vco 266 mhz note: this table results from the allowed range for f vco , which is f loop modified by clkctrl[rng].
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 22 2.5.2.5 core clock frequency range when using ddr memory the core clock can also be limited by the frequency range of the ddr devices in the system. table 13 summarizes this restriction. 2.5.3 reset timing the MSC7113 device has several inputs to the reset logic. all MSC7113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. th e reset status register indicates the most recent sources to ca use a reset. table 14 describes the reset sources. table 15 summarizes the reset actions that occur as a result of the different reset sources. table 12. resulting ranges permitted for the core clock clkctrl[cksel] clkctrl[rng] resulting division factor allowed range of core clock comments 11 1 1 reserved reserved 11 0 2 133 core clock 266 mhz limited by range of pll 01 1 2 133 core clock 266 mhz limited by range of pll 01 0 4 66.5 core clock 133 mhz limited by range of pll note: this table results from the allowed range for f out , which depends on clock selected via clkctrl[cksel]. table 13. core clock ranges when using ddr ddr type allowed frequency range for ddr ck corresponding range for the core clock comments ddr 200 (pc-1600) 83?100 mhz 166 core clock 200 mhz core limited to 2 maximum ddr frequency ddr 266 (pc-2100) 83?133 mhz 166 core clock 266 mhz core limited to 2 maximum ddr frequency ddr 333 (pc-2600) 83?150 mhz 166 core clock 300 mhz core limited to 2 maximum ddr frequency table 14. reset sources name direction description power-on reset (poreset ) input initiates the power-on reset flow that resets the MSC7113 and configures various attributes of the MSC7113. on poreset , the entire MSC7113 device is reset. spll and dll states are reset, hreset is driven, the sc1400 extended core is reset, and system configuration is sampled. the system is configured only when poreset is asserted. external hard reset (hreset ) input/ output initiates the hard reset flow that configures various attributes of the MSC7113. while hreset is asserted, hreset is an open-drain output. upon hard reset, hreset is driven and the sc1400 extended core is reset. software watchdog reset internal when the MSC7113 watchdog count reaches zero, a software watchdog reset is signalled. the enabled software watchdog event then gener ates an internal hard reset sequence. bus monitor reset internal when the MSC7113 bus monitor count reaches zero, a bus monitor hard reset is asserted. the enabled bus monitor event then generates an internal hard reset sequence. jtag extest, clamp, or highz command internal when a test access port (tap) executes an extest, clamp, or highz command, the tap logic asserts an internal reset signal that generates an internal soft reset sequence.
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 23 2.5.3.1 power-on reset (poreset ) pin asserting poreset initiates the power-on reset flow. poreset must be asserted externally for at least 16 clkin cycles after external power to the MSC7113 reaches at least 2/3 v dd . 2.5.3.2 reset configuration the MSC7113 has two mechanisms for writing the reset configuration: ? from a host through the host interface (hdi16) ? from memory through the i 2 c interface five signal levels (see chapter 1 for signal description details) are sampled on poreset deassertion to define the boot and operating conditions: ? bm[0?1] ? swte ?h8bit ? hdsp 2.5.3.3 reset timing tables table 16 and figure 4 describe the reset timing for a reset configuration write. table 15. reset actions for each reset source reset action/reset source power-on reset (poreset ) hard reset (hreset ) soft reset (sreset ) external only external or internal (software watchdog or bus monitor) jtag command: extest, clamp, or highz configuration pins sampled (refer to section 2.5.3.1 for details) . yes no no pll and clock synthesis states reset yes no no hreset driven yes yes no software watchdog and bus time-out monitor registers yes yes yes clock synthesis modules (stopctrl, hltreq, and hltack) reset yes yes yes extended core reset yes yes yes peripheral modules reset yes yes yes table 16. timing for a reset configuration write no. characteristics expression unit 1 required external poreset duration minimum 16/f clkin clocks 2 delay from poreset deassertion to hreset deassertion 521/f clkin clocks note: timings are not tested, but are guaranteed by design.
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 24 2.5.4 ddr dram controller timing this section provides the ac electrical characteristics for the ddr dram interface. 2.5.4.1 ddr dram input ac timing specifications table 17 provides the input ac timing specifications for the ddr dram interface. figure 4. timing diagram for a reset configuration write table 17. ddr dram input ac timing no. parameter symbol min max unit mask set 1l44x mask set 1m88b ? ac input low voltage v il ?v ref ? 0.31 v ref ? 0.31 v ? ac input high voltage v ih v ref + 0.31 v ddm + 0.3 v ddm + 0.3 v 201 maximum dn input setup skew relative to dqsn input ? ? 1026 900 ps 202 maximum dn input hold skew relative to dqsn input ? ? 386 900 ps notes: 1. maximum possible skew between a data strobe (dqsn) and any corresponding bit of data (d[8n + {0...7}] if 0 n 7). 2. see table 18 for t ck value. 3. dn should be driven at the same time as dqsn. this is nec essary because the dqsn centering on the dqn data tenure is done internally. figure 5. ddr dram input timing diagram poreset poreset internal hreset input output (i/o) configuration pins are sampled 2 1 dn dqsn d1 d0 201 202 202 201 note : dqs centering is done internally.
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 25 2.5.4.2 ddr dram output ac timing specifications table 18 and table 19 list the output ac timing specifications and m easurement conditions for the ddr dram interface. table 18. ddr dram output ac timing no. parameter symbol min max unit mask set 1l44x mask set 1m88b 200 ck cycle time, (ck/ck crossing) 1 ? 100 mhz (ddr200) ? 133 mhz (ddr266) t ck 10 not applicable 1.0 7.52 ? ? ns ns 204 an/ras /cas /we /cke output setup with respect to ck t ddkhas 0.5 t ck ? 2250 0.5 t ck ? 1000 ? ps 205 an/ras /cas /we /cke output hold with respect to ck t ddkhax 0.5 t ck ? 1250 0.5 t ck ? 1000 ? ps 206 c sn output setup with respect to ck t ddkhcs 0.5 t ck ? 2250 0.5 t ck ? 1000 ? ps 207 c sn output hold with respect to ck t ddkhcx 0.5 t ck ? 1250 0.5 t ck ? 1000 ? ps 208 ck to dqsn 2 t ddkhmh ?600 ?600 600 ps 209 dn/dqmn output setup with respect to dqsn 3 t ddkhds, t ddklds 0.25 t mck ? 1050 0.25 t ck ? 750 ? ps 210 dn/dqmn output hold with respect to dqsn 3 t ddkhdx, t ddkldx 0.25 t ck ? 1050 0.25 t ck ? 750 ? ps 211 dqsn preamble start 4 t ddkhmp ?0.25 t ck ?0.25 t ck ?ps 212 dqsn epilogue end 5 t ddkhme ?600 ?600 600 ps notes: 1. all ck/ck referenced measurements are made from the crossing of the two signals 0.1 v. 2. t ddkhmh can be modified through the tcfg2[wrdd] dqss override bi ts. the dram requires that the first write data strobe arrives 75?125% of a dram cycle after the write command is issued. any skew between dqsn and ck must be considered when trying to achieve this 75%?125% goal. the tcfg2[wrdd] bits can be used to shift dqsn by 1/4 dram cycle increments. the skew in this case refers to an internal skew existing at the signal connections. by default, the ck/ck crossing occurs in the middle of the control signal (an/ras /cas /we /cke) tenure. setting tcfg2[acsm] bit shifts the control signal assertion 1/2 dram cycle earlier than the default timing. this m eans that the signal is assert ed no earlier than 410 ps before the ck/ck crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval from ?410 to +677 ps). timing is verified by refer encing the falling edge of ck. see chapter 10 of the msc711x reference manual for details. 3. determined by maximum possible skew between a data strobe (dqs) and any corresponding bit of data. the data strobe should be centered inside of the data eye. 4. please note that this spec is in reference to the dqsn first rising edge. it could also be referenced from ck(r), but due to programmable delay of the writ e strobes (tcfg2[wrdd]), ther e pre-amble may be extended for a full dram cycle. for this reason, we reference from dqsn. 5. all outputs are referenced to the rising edge of ck. note that th is is essentially the ck/dqsn skew in spec 208. in addition there is no real ?maximum? time for the epilogue end. jedec does not require this is as a device limitation, but simply for the chip to guarantee fast enough write to read turn-around times. this is already guaranteed by the memory controller operation.
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 26 figure 6 shows the ddr dram output timing diagram. figure 7 provides the ac test load for the ddr dram bus. 2.5.5 tdm timing figure 6. ddr dram output timing diagram figure 7. ddr dram ac test load table 19. ddr dram measurement conditions symbol ddr dram unit v th 1 v ref 0.31 v v v out 2 0.5 v ddm v notes: 1. data input threshold measurement point. 2. data output measurement point. table 20. tdm timing no. characteristic expression min max units 300 tdmxrck/tdmxtck tc 20.0 ? ns 301 tdmxrck/tdmxtck high pulse width 0.4 tc 8.0 ? ns 302 tdmxrck/tdmxtck low pulse width 0.4 tc 8.0 ? ns 303 tdm all input setup time 3.0 ? ns 304 tdmxrd hold time 3.5 ? ns 305 tdmxtfs/tdmxrfs input hold time 2.0 ? ns 306 tdmxtck high to tdmxtd output active 4.0 ? ns an dn dqsn ck ck d1 d0 write a0 noop ras cas we cke 200 208 209 209 212 210 210 211 206 204 207 205 dqmn output z 0 = 50 v out r l = 50
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 27 307 tdmxtck high to tdmxtd output valid ? 14.0 ns 308 tdmxtd hold time 2.0 ? ns 309 tdmxtck high to tdmxtd output high impedance ? 10.0 ns 310 tdmxtfs/tdmxrfs output valid ? 13.5 ns 311 tdmxtfs/tdmxrfs output hold time 2.5 ? ns notes: 1. output values are based on 30 pf capacitive load. 2. inputs are referenced to the sampling that the tdm is program med to use. outputs are refe renced to the programming edge they are programmed to use. use of the rising edge or falling edge as a reference is programmable. refer to the msc711x reference manual for details. tdmxtck and tdmxrck are shown using the rising edge. figure 8. tdm receive signals figure 9. tdm transmit signals table 20. tdm timing no. characteristic expression min max units tdmxrck tdmxrd tdmxrfs 300 301 302 303 303 304 305 311 310 tdmxrfs (output) ~ ~ tdmxtck tdmxtd ~ ~ ~ ~ 306 307 309 308 300 301 302 311 310 tdmxrck tdmxtfs (output) tdmxtfs (input) 303 305
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 28 2.5.6 ethernet timing 2.5.6.1 receive signal timing table 21. receive signal timing no. characteristics min max unit 800 receive clock period: ? mii: rxclk (max frequency = 25 mhz) ? rmii: refclk (max frequency = 50 mhz) 40 20 ? ? ns ns 801 receive clock pulse width high?as a percent of clock period ? mii: rxclk ? rmii: refclk 35 14 7 65 ? ? % ns ns 802 receive clock pulse width low?as a percent of clock period: ? mii: rxclk ? rmii: refclk 35 14 7 65 ? ? % ns ns 803 rxdn, rx_dv, crs_dv, rx_er to receive clock rising edge setup time 4 ? ns 804 receive clock rising edge to rxdn, rx_dv, crs_dv, rx_er hold time 2 ? ns figure 10. ethernet receive signal timing valid receive rx_dv rxdn rx_er 803 804 clock 800 802 801 crs_dv
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 29 2.5.6.2 transmit signal timing 2.5.6.3 asynchronous input signal timing table 22. transmit signal timing no. characteristics min max unit 800 transmit clock period: ? mii: txclk ? rmii: refclk 40 20 ? ? ns ns 801 transmit clock pulse width high?as a percent of clock period ? mii: rxclk ? rmii: refclk 35 14 7 65 ? ? % ns ns 802 transmit clock pulse width low?as a percent of clock period: ? mii: rxclk ? rmii: refclk 35 14 7 65 ? ? % ns ns 805 transmit clock to txdn, tx_en, tx_er invalid 4 ? ns 806 transmit clock to txdn, tx_en, tx_er valid ? 14 ns figure 11. ethernet receive signal timing table 23. asynchronous input signal timing no. characteristics min max unit 807 ? mii: crs and col minimum pulse width (1.5 txclk period) ? rmii: crs_dv minimum pulse width (1.5 x refclk period) 60 30 ? ? ns ns figure 12. asynchronous input signal timing valid transmit tx_en txdn tx_er 805 806 clock 800 801 802 crs col 807 crs_dv
MSC7113 data sheet, rev. 11 electrical characteristics freescale semiconductor 30 2.5.6.4 management interface timing table 24. ethernet controller management interface timing no. characteristics min max unit 808 mdc period 400 ? ns 809 mdc pulse width high 160 ? ns 810 mdc pulse width low 160 ? ns 811 mds falling edge to mdio output invalid (minimum propagation delay) 0 ? ns 812 mds falling edge to mdio output valid (maximum propagation delay) ? 15 ns 813 mdio input to mdc rising edge setup time 10 ? ns 814 mdc rising edge to mdio input hold time 10 ? ns figure 13. serial management channel timing mdc (output) mdio (output) mdio (input) 809 808 810 811 812 814 813
electrical characteristics MSC7113 data sheet, rev. 11 freescale semiconductor 31 2.5.7 hdi16 signals table 25. host interface (hdi16) timing 1, 2 no. characteristics 3 mask set 1l44x mask set 1m88b unit expression value expression value 40 host interface clock period t hclk note 1 t core note 1 ns 44a read data strobe minimum assertion width 4 hack read minimum assertion width 3.0 t hclk note 11 2.0 t core + 9.0 note 11 ns 44b read data strobe minimum deassertion width 4 hack read minimum deassertion width 1.5 t hclk note 11 1.5 t core note 11 ns 44c read data strobe minimum deassertion width 4 after ?last data register? reads 5,6 , or between two consecutive cvr, icr, or isr reads 7 hack minimum deassertion width after ?last data register? reads 5,6 2.5 t hclk note 11 2.5 t core note 11 ns 45 write data strobe minimum assertion width 8 hack write minimum assertion width 1.5 t hclk note 11 1.5 t core note 11 ns 46 write data strobe minimum deassertion width 8 hack write minimum deassertion width after icr, cvr and data register writes 5 2.5 t hclk note 11 2.5 t core note 11 ns 47 host data input minimum setup time before write data strobe deassertion 8 host data input minimum setup time before hack write deassertion ?3.0?2.5ns 48 host data input minimum hold time after write data strobe deassertion 8 host data input minimum hold time after hack write deassertion ?4.0?2.5ns 49 read data strobe minimum assertion to output data active from high impedance 4 hack read minimum assertion to output data active from high impedance ?1.0?1.0ns 50 read data strobe maximum assertion to output data valid 4 hack read maximum assertion to output data valid (2.0 t hclk ) + 8.0 note 11 (2.0 t core ) + 8.0 note 11 ns 51 read data strobe maximum deassertion to output data high impedance 4 hack read maximum deassertion to output data high impedance ?8.0?9.0ns 52 output data minimum hold time after read data strobe deassertion 4 output data minimum hold time after hack read deassertion ? 1.0 ? 1.0 ns 53 hcs[1?2] minimum assertion to read data strobe assertion 4 ?0.0?0.5ns 54 hcs[1?2] minimum assertion to write data strobe assertion 8 ?0.0?0.0ns 55 hcs[1?2] maximum assertion to output data valid (2.0 t hclk ) + 8.0 note 11 (2.0 t core ) + 6.0 note 11 ns 56 hcs[1?2] minimum hold time after data strobe deassertion 9 ?0.0?0.5ns 57 ha[0?3], hrw minimum setup time before data strobe assertion 9 ?5.0?5.0ns 58 ha[0?3], hrw minimum hold time after data strobe deassertion 9 ?5.0?5.0ns 61 maximum delay from read data strobe deassertion to host request deassertion for ?last data register? read 4, 5, 10 (3.0 t hclk ) + 8.0 note 11 (3.0 t core ) + 6.0 note 11 ns 62 maximum delay from write data strobe deassertion to host request deassertion for ?last data register? write 5,8,10 (3.0 t hclk ) + 8.0 note 11 (3.0 t core ) + 6.0 note 11 ns 63 minimum delay from dma hack (oad=0) or read/write data strobe(oad=1) deassertion to hreq assertion. (2.0 t hclk ) + 1.0 note 11 (2.0 t core ) + 1.0 note 11 ns 64 maximum delay from dma hack (oad=0) or read/write data strobe(oad=1) assertion to hreq deassertion (5.0 t hclk ) + 8.0 note 11 (5.0 t core ) + 6.0 note 11 ns
MSC7113 data sheet, rev. 11 freescale semiconductor 32 figure 14 and figure 15 show hdi16 read signal timing. figure 16 and figure 17 show hdi16 write signal timing. notes: 1. t hclk = 2/ (core clock). at 200 mhz, t hclk = 10 ns. t core = core clock period. at 266 mhz, t core = 3.75 ns. 2. in the timing diagrams below, the controls pins are dr awn as active low. the pi n polarity is programmable. 3. v dd = 3.3 v 0.15 v; t j = ?40c to +105 c, c l = 30 pf for maximum delay timings and c l = 0 pf for minimum delay timings. 4. the read data strobe is hrd /hrd in the dual data strobe mode and hds /hds in the single data strobe mode. 5. for 64-bit transfers, the ?last data register? is the register at address 0x7, which is the last location to be read or written in data transfers. this is rx0/tx0 in the little endian mode (hbe = 0), or rx3/tx3 in the big endian mode (hbe = 1). 6. this timing is applicable only if a read from the ?last data regist er? is followed by a read from the rxl, rxm, or rxh register s without first polling rxdf or hreq bits, or waiting for the assertion of the hreq /hreq signal. 7. this timing is applicable only if two consecutiv e reads from one of these registers are executed. 8. the write data strobe is hwr in the dual data strobe mode and hds in the single data strobe mode. 9. the data strobe is host read (hrd /hrd) or host write (hwr /hwr) in the dual data strobe mode and host data strobe (hds /hds) in the single data strobe mode. 10. the host request is hreq /hreq in the single host request mode and hrrq /hrrq and htrq /htrq in the double host request mode. hrrq /hrrq is deasserted only when hotx fifo is empty, htrq /htrq is deasserted only if horx fifo is full (treat as level host request). 11. compute the value using the expression. 12. for mask set 1m88b, the read and write data strobe minimum deasse rtion width for non-?last data register? accesses in single and dual data strobe modes is based on timings 57 and 58. figure 14. read timing diagram, single data strobe table 25. host interface (hdi16) timing 1, 2 (continued) no. characteristics 3 mask set 1l44x mask set 1m88b unit expression value expression value hds ha[0?3] hcs[1?2] hd[0?15] 50 55 44c 44a 53 52 58 57 51 49 61 56 hreq (single host request) hrw 57 58 hrrq (double host request)
MSC7113 data sheet, rev. 11 freescale semiconductor 33 figure 15. read timing diagram, double data strobe figure 16. write timing diagram, single data strobe hrd ha[0?3] hcs[1?2] hd[0?15] 50 55 44a 44a 53 52 58 57 51 49 56 61 hreq (single host request) hrrq (double host request) hds ha[0?3] hcs[1?2] hd[0?15] 47 46 45 54 58 57 56 hrw 57 58 48 62 hreq (single host request) htrq (double host request)
MSC7113 data sheet, rev. 11 freescale semiconductor 34 figure 17. write timing diagram, double data strobe figure 18. host dma read timing diagram, hpcr[oad] = 0 hwr ha[0?3] hcs[1?2] hd[0?15] 47 46 45 54 48 58 57 56 62 hreq (single host request) htrq (double host request) rx[0?3] read data valid 64 44a 63 44b 51 50 49 52 (output) hreq hack hd[0?15] (output)
MSC7113 data sheet, rev. 11 freescale semiconductor 35 figure 19. host dma write timing diagram, hpcr[oad] = 0 tx[0?3] write data valid 63 64 46 45 47 48 (output) hreq hack hd[0?15] (input)
MSC7113 data sheet, rev. 11 freescale semiconductor 36 2.5.8 i 2 c timing table 26. i 2 c timing no. characteristic fast unit min max 450 scl clock frequency 0 400 khz 451 hold time start condition (clock period/2) ? 0.3 ? s 452 scl low period (clock period/2) ? 0.3 ? s 453 scl high period (clock period/2) ? 0.1 ? s 454 repeated start set-up time (not shown in figure) 2 1/f bck ? s 455 data hold time 0 ? s 456 data set-up time 250 ? ns 457 sda and scl rise time ? 700 ns 458 sda and scl fall time ? 300 ns 459 set-up time for stop (clock period/2) ? 0.7 ? s 460 bus free time between stop and start (clock period/2) ? 0.3 ? s note: sda set-up time is referenced to the rising edge of scl. sda hold time is referenced to the falling edge of scl. load capacitan ce on sda and scl is 400 pf. figure 20. i 2 c timing diagram scl sda data byte start condition stop condition a c k 78 9 456 1 2 3 start condition 458 458 457 457 460 459 451 452 453 scl sda data byte start condition
MSC7113 data sheet, rev. 11 freescale semiconductor 37 2.5.9 uart timing 2.5.10 ee timing figure 23 shows the signal behavior of the ee pin. table 27. uart timing no. characteristics expression mask set 1l44x mask set 1m88b unit min max min max ? internal bus clock (apbclk) f core /2 ? 100 ? 133 mhz ? internal bus clock period (1/apbclk) t apbclk 10.0 ? 7.52 ? ns 400 urxd and utxd inputs high/low duration 16 t apbclk 160.0 ? 120.3 ? ns 401 urxd and utxd inputs rise/fall time ? 5 ? 5 ns 402 utxd output rise/fall time ? 5 ? 5 ns figure 21. uart input timing figure 22. uart output timing table 28. ee0 timing number characteristics type min 65 ee0 input to the core asynchronous 4 core clock periods 66 ee0 output from the core synchronous to core clock 1 core clock period notes: 1. the core clock is the sc1400 core clock. the ratio between t he core clock and clkout is configured during power-on-reset. 2. configure the direction of the ee pin in the ee_ctrl register (see the sc1400 core reference manual for details. 3. refer to table 14 for details on ee pin functionality. figure 23. ee pin timing utxd, urxd 400 inputs 400 401 401 utxd output 402 402 ee0 in 65 ee0 out 66
MSC7113 data sheet, rev. 11 freescale semiconductor 38 2.5.11 event timing figure 24 shows the signal behavior of the evnt pin. 2.5.12 gpio timing figure 25 shows the signal behavior of the gpi/gpo pin. table 29. evnt signal timing number characteristics type min 67 evnt as input asynchronous 1.5 apbclk periods 68 evnt as output synchronous to core clock 1 apbclk period notes: 1. refer to table 27 for a definition of the apbclk period. 2. direction of the evnt signal is configur ed through the gpio and event port registers. 3. refer to the msc711x reference manual for details on evnt pin functionality. figure 24. evnt pin timing table 30. gpio signal timing 1,2,3 number characteristics type min 601 gpi 4.5 asynchronous 1.5 apbclk periods 602 gpo 5 synchronous to core clock 1 apbclk period 603 port a edge-sensitive interrupt asynchronous 1.5 apbclk periods 604 port a level-sensitive interrupt asynchronous 3 apbclk periods 6 notes: 1. refer to table 27 for a definition of the apbclk period. 2. direction of the gpio signal is conf igured through the gpio port registers. 3. refer to msc711x reference manual for details on gpio pin functionality. 4. gpi data is synchronized to the apbclk internally and the minimum listed is the capability of the hardware to capture data into a register when the gpa_dr is read. the specification is not tested due to the asynchronous nature of the input and dependence on the state of the dsp core. it is guaranteed by design. 5. the input and output signals cannot toggle faster than 50 mhz. 6. level-sensitive interrupts should be held low until the system dete rmines (via the service routine) that the interrupt is acknowledged. figure 25. gpi/gpo pin timing evnt in 67 evnt out 68 gpi 601 gpo 602
MSC7113 data sheet, rev. 11 freescale semiconductor 39 2.5.13 jtag signals table 31. jtag timing no. characteristics all frequencies unit min max 700 tck frequency of operation (1/(t c 3); maximum 22 mhz) 0.0 40.0 mhz 701 tck cycle time 25.0 ? ns 702 tck clock pulse width measured at v m = 1.6 v 11.0 ? ns 703 tck rise and fall times 0.0 3.0 ns 704 boundary scan input data set-up time 5.0 ? ns 705 boundary scan input data hold time 14.0 ? ns 706 tck low to output data valid 0.0 20.0 ns 707 tck low to output high impedance 0.0 20.0 ns 708 tms, tdi data set-up time 5.0 ? ns 709 tms, tdi data hold time 25.0 ? ns 710 tck low to tdo data valid 0.0 24.0 ns 711 tck low to tdo high impedance 0.0 10.0 ns 712 trst assert time 100.0 ? ns note: all timings apply to oce module data transfers as t he oce module uses the jtag port as an interface. figure 26. test clock input timing diagram tck (input) v m v m v ih v il 701 702 703 703
MSC7113 data sheet, rev. 11 freescale semiconductor 40 figure 27. boundary scan (jtag) timing diagram figure 28. test access port timing diagram figure 29. trst timing diagram tck (input) data inputs data outputs data outputs v ih v il input data valid output data valid 705 704 706 707 tck (input) tdi (input) tdo (output) tdo (output) v ih v il input data valid output data valid tms 708 709 710 711 trst (input) 712
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 41 3 hardware design considerations this section described various areas to consider when incorporating the MSC7113 device into a system design. 3.1 thermal design considerations an estimation of the chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (r ja p d )eqn.1 where t a = ambient temperature near the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = p int + p i/o = power dissipation in the package (w) p int = i dd v dd = internal power dissipation (w) p i/o = power dissipated from device on output pins (w) the power dissipation values for the MSC7113 are listed in table 4 . the ambient temperature for the device is the air temperature in the immediate vicinity th at would cool the device. the junction-to -ambient thermal resistances are jedec standard values that provide a quick and easy estimation of th ermal performance. there are two values in common usage: the value determined on a single layer board and the value obtain ed on a board with two planes. the value that more closely approximates a specific application depends on the power dissipat ed by other components on the printed circuit board (pcb). the value obtained using a single layer board is appropriate fo r tightly packed pcb configuratio ns. the value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 w/cm 2 with natural convection) and well separated components. based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. if t j appears to be too high, either lower the ambient temperature or the power dissipation of the chip. you can verify the junction temperature by measuring the case temperature using a sm all diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case. use the following equation to determine t j : t j = t t + ( jt p d )eqn.2 where t t = thermocouple (or infrared) temp erature on top of the package ( c) jt = thermal characterization parameter ( c/w) p d = power dissipation in the package (w)
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 42 3.2 power supply design considerations this section outlines the MSC7113 power considerations: power supply, power sequencing, power planes, decoupling, power supply filtering, and power consumption. it also presents a recommended power supply design and options for low-power consumption. for information on ac /dc electrical specifications and thermal characteristics, refer to section 2 . 3.2.1 power supply the MSC7113 requires four input voltages, as shown in table 32 . you should supply the MSC7113 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. the core voltage is supplied with 1.2 v (+5% and ?10%) across v ddc and gnd and the i/o section is supplied with 3.3 v ( 10%) across v ddio and gnd. the memory and reference voltages supply the ddr memory controller block. the memory voltage is supplied with 2.5 v across v ddm and gnd . the reference voltage is supplied across v ref and gnd and must be between 0.49 v ddm and 0.51 v ddm . refer to the jedec standard jesd8 ( stub series terminated logic for 2.5 volts (sttl_2)) for memory voltage supply requirements. 3.2.2 power sequencing one consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied . the rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. it is extremely important to observe the power up and power down se quences at the board level to avoid latch-up, forward biasing of esd devices, and excessive currents, which all lead to severe device damage. note: there are five possible power-up/power-down sequence cases. th e first four cases listed in the following sections are recommended for new designs. the fifth case is not recomme nded for new designs and must be carefully evaluated for current spike risks based on actual information for the specific application. table 32. MSC7113 voltages voltage symbol value core v ddc 1.2 v memory v ddm 2.5 v reference v ref 1.25 v i/o v ddio 3.3 v
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 43 3.2.2.1 case 1 the power-up sequence is as follows: 1. turn on the v ddio (3.3 v) supply first. 2. turn on the v ddc (1.2 v) supply second. 3. turn on the v ddm (2.5 v) supply third. 4. turn on the v ref (1.25 v) supply fourth (last). the power-down sequence is as follows: 1. turn off the v ref (1.25 v) supply first. 2. turn off the v ddm (2.5 v) supply second. 3. turn off the v ddc (1.2 v) supply third. 4. turn of the v ddio (3.3 v) supply fourth (last). use the following guidelines: ? make sure that the time interv al between the ramp-down of v ddio and v ddc is less than 10 ms. ? make sure that the time interval be tween the ramp-up or ramp-down for v ddc and v ddm is less than 10 ms for power-up and power-down. ? refer to figure 30 for relative timing for power sequencing case 1. figure 30. voltage sequencing case 1 time voltage ramp-down ramp-up v ddio = 3.3 v v ddm = 2.5 v v ddc = 1.2 v v ref = 1.25 v <10 ms <10 ms <10 ms <10 ms
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 44 3.2.2.2 case 2 the power-up sequence is as follows: 1. turn on the v ddio (3.3 v) supply first. 2. turn on the v ddc (1.2 v) and v ddm (2.5 v) supplies simultaneously (second). 3. turn on the v ref (1.25 v) supply last (third). note: make sure that the time interval between the ramp-up of v ddio and v ddc /v ddm is less than 10 ms. the power-down sequence is as follows: 1. turn off the v ref (1.25 v) supply first. 2. turn off the v ddm (2.5 v) supply second. 3. turn off the v ddc (1.2 v) supply third. 4. turn of the v ddio (3.3 v) supply fourth (last). use the following guidelines: ? make sure that the time interv al between the ramp-down for v ddio and v ddc is less than 10 ms. ? make sure that the time interval be tween the ramp-up or ramp-down for v ddc and v ddm is less than 10 ms for power-up and power-down. ? refer to figure 31 for relative timing for case 2. figure 31. voltage sequencing case 2 time voltage ramp-down ramp-up v ddio = 3.3 v v ddm = 2.5 v v ddc = 1.2 v v ref = 1.25 v <10 ms <10 ms <10 ms
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 45 3.2.2.3 case 3 the power-up sequence is as follows: 1. turn on the v ddio (3.3 v) supply first. 2. turn on the v ddc (1.2 v) supply second. 3. turn on the v ddm (2.5 v) and v ref (1.25 v) supplies simultaneously (third). note: make sure that the time interval between the ramp-up of v ddio and v ddc is less than 10 ms. the power-down sequence is as follows: 1. turn off the v ddm (2.5 v) and v ref (1.25 v) supplies simultaneously (first). 2. turn off the v ddc (1.2 v) supply second. 3. turn of the v ddio (3.3 v) supply third (last). use the following guidelines: ? make sure that the time interv al between the ramp-down for v ddio and v ddc is less than 10 ms. ? make sure that the time interval between the ramp-up or ramp-down time for v ddc and v ddm is less than 10 ms for power-up and power-down. ? refer to figure 32 for relative timing for case 3. figure 32. voltage sequencing case 3 time voltage ramp-down ramp-up v ddio = 3.3 v v ddm = 2.5 v v ddc = 1.2 v v ref = 1.25 v <10 ms <10 ms <10 ms <10 ms
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 46 3.2.2.4 case 4 the power-up sequence is as follows: 1. turn on the v ddio (3.3 v) supply first. 2. turn on the v ddc (1.2 v), v ddm (2.5 v), and v ref (1.25 v) supplies simultaneously (second). note: make sure that the time interval between the ramp-up of v ddio and v ddc is less than 10 ms. the power-down sequence is as follows: 1. turn off the v ddc (1.2 v), v ref (1.25 v), and v ddm (2.5 v) supplies simultaneously (first). 2. turn of the v ddio (3.3 v) supply last. use the following guidelines: ? make sure that the time interval between the ramp-up or ramp-down time for v ddc and v ddm is less than 10 ms for power-up and power-down. ? refer to figure 33 for relative timing for case 4. figure 33. voltage sequencing case 4 time voltage ramp-down ramp-up v ddio = 3.3 v v ddm = 2.5 v v ddc = 1.2 v v ref = 1.25 v <10 ms <10 ms
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 47 3.2.2.5 case 5 (not recommended for new designs) the power-up sequence is as follows: 1. turn on the v ddio (3.3 v) supply first. 2. turn on the v ddm (2.5 v) supply second. 3. turn on the v ddc (1.2 v) supply third. 4. turn on the v ref (1.25 v) supply fourth (last). note: make sure that the time interval between the ramp-up of v ddio and v ddm is less than 10 ms. the power-down sequence is as follows: 1. turn off the v ref (1.25 v) supply first. 2. turn off the v ddc (1.2 v) supply second. 3. turn off the v ddm (2.5 v) supply third. 4. turn of the v ddio (3.3 v) supply fourth (last). use the following guidelines: ? make sure that the time interv al between the ramp-down of v ddio and v ddm is less than 10 ms. ? make sure that the time interval be tween the ramp-up or ramp-down for v ddc and v ddm is less than 2 ms for power-up and power-down. ? refer to figure 34 for relative timing for power sequencing case 5. note: cases 1, 2, 3, and 4 are recommended for system design. de signs that use case 5 may have large current spikes on the v ddm supply at startup and is not recommended for most designs. if a design uses case 5, it must accommodate the potential current spikes. verify risks related to current spikes using actual information for the specific application. figure 34. voltage sequencing case 5 time voltage ramp-down ramp-up v ddio = 3.3 v v ddm = 2.5 v v ddc = 1.2 v v ref = 1.25 v <10 ms <2 ms <2 ms <10 ms
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 48 3.2.3 power planes each power supply pin ( v ddc , v ddm, and v ddio ) should have a low-impedance path to the board power supply. each gnd pin should be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on the device. the MSC7113 v ddc power supply pins should be bypassed to ground using decoupling capacitors. the capacitor leads and associated printed circuit traces connecting to device power pins and gnd should be kept to less than half an inch per capacitor lead. a minimum four-layer board that employs two inner layers as power and gnd planes is recommended. see section 3.5 for ddr controller power guidelines. 3.2.4 decoupling both the i/o voltage and core voltage should be decoupled fo r switching noise. for i/o decoupling, use standard capacitor values of 0.01 f for every two to three voltage pins. for core voltage d ecoupling, use two levels of decoupling. the first level should consist of a 0.01 f high frequency capacitor with low effective series resistance (esr) and effective series inductance (esl) for every two to three voltage pins. the second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 f and one 47 f, (with low esr and esl) mounted as closely as possible to the MSC7113 voltage pins. additionally, the maximum drop between the power supply and the dsp device should be 15 mv at 1 a. 3.2.5 pll power supply filtering the MSC7113 v ddpll power signal provides power to the clock generation p ll. to ensure stability of the internal clock, the power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. v ddpll can be connected to v ddc through a 2 resistor. v sspll can be tied directly to the gnd plane. a circuit similar to the one shown in figure 35 is recommended. the pll loop filter should be placed as closely as possible to the v ddpll pin (which are located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.the 0.01 f capacitor should be closest to v ddpll , followed by the 0.1 f capacitor, th e 10 f capacitor, and finally the 2- resistor to v ddc . these traces should be kept short. 3.2.6 power consumption you can reduce power consumption in your design by controllin g the power consumption of the following regions of the device: ? extended core. use the sc1400 stop and wait modes by issuing a stop or wait instruction. ? clock synthesis module. disable the pll, timer, watchdog, or ddr clocks or disable the clko pin. ? ahb subsystem. freeze or shut down the ahb subsystem using the gpsctl[xbr_hrq] bit. ? peripheral subsystem. halt the individual on-device peripherals such as the ddr memory controller, ethernet mac, hdi16, tdm, uart, i 2 c, and timer modules. for details, see the ?clocks and power management? chapter of the msc711x reference manual . figure 35. pll power supply filter circuits v ddc v ddpll 2 0.1 f 0.01 f 10 f
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 49 3.2.7 power supply design one of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. for the system i/o voltage supply, a simple fixed 3.3 v supply can be used. however, a separate adjustable linear regulator supply for the core voltage v ddc should be implemented. for the memory power supply, re gulators are available that take care of all ddr power requirements. 3.3 estimated power usage calculations the following equations permit estimated power usage to be cal culated for individual design conditions. overall power is derived by totaling the power used by each of the major subsystems: p total = p core + p peripherals + p ddrio + p io + p leakage eqn. 3 this equation combines dynamic and static power. dyna mic power is determined using the generic equation: c v 2 f 10 ?3 mw eqn. 4 where, c = load capacitance in pf v = peak-to-peak voltage swing in v f = frequency in mhz 3.3.1 core power estimation of core power is straightforward. it uses the ge neric dynamic power equation and assumes that the core load capacitance is 750 pf, core voltage swing is 1.2 v, and th e core frequency is 200 mhz or 266 mhz. this yields: p core = 750 pf (1.2 v) 2 200 mhz 10 ?3 = 216 mw eqn. 5 p core = 750 pf (1.2 v) 2 266 mhz 10 ?3 = 287 mw eqn. 6 this equation allows for adjustments to voltage and frequency if necessary. table 33. recommended power supply ratings supply symbol nominal voltage current rating core v ddc 1.2 v 1.5 a per device memory v ddm 2.5 v 0.5 a per device reference v ref 1.25 v 10 a per device i/o v ddio 3.3 v 1.0 a per device
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 50 3.3.2 peripheral power peripherals include the ddr memory co ntroller, dma controller, hdi16, tdm, uart, timers, gpios, and the i 2 c module. basic power consumption by each module is assumed to be th e same and is computed by us ing the following equation which assumes an effective load of 20 pf, core voltage swing of 1.2 v, and a switching frequency of 100 mh or 133 mhz. this yields: p peripheral = 20 pf (1.2 v) 2 100 mhz 10 ?3 = 2.88 mw per peripheral eqn. 7 p peripheral = 20 pf (1.2 v) 2 133 mhz 10 ?3 = 3.83 mw per peripheral eqn. 8 multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption. 3.3.3 external memory power estimation of power consumption by the ddr memory system is comp lex. it varies based on overall system signal line usage, termination and load levels, and switching rates. because the ddr memory includes terminatio ns external to the MSC7113 device, the 2.5 v power source provides the power for the terminatio n, which is a static value of 16 ma per signal driven high. the dynamic power is computed, however, using a differential voltage swing of 0.200 v, yielding a peak-to-peak swing of 0.4 v. the equations for computing the ddr power are: p ddrio = p static + p dynamic eqn. 9 p static = (unused pins % driven high) 16 ma 2.5 v eqn. 10 p dynamic = (pin activity value) 20 pf (0.4 v) 2 200 mhz 10 ?3 mw eqn. 11 p dynamic = (pin activity value) 20 pf (0.4 v) 2 266 mhz 10 ?3 mw eqn. 12 pin activity value = (active data lines % activity % data switching) + (active address lines % activity) eqn. 13 as an example, assume the following: unused pins = 16 (ddr uses 16-pin mode) % driven high = 50% active data lines = 16 % activity = 60% % data switching = 50% active address lines = 3 in this example, the ddr memory power consumption is: p ddrio = ((16 0.5) 16 2.5) + (((16 0.6 0.5) + (3 0.6)) 20 (0.4) 2 200 10 ?3 ) = 324.2 mw eqn. 14 p ddrio = ((16 0.5) 16 2.5) + (((16 0.6 0.5) + (3 0.6)) 20 (0.4) 2 266 10 ?3 ) = 326.3 mw eqn. 15
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 51 3.3.4 external i/o power the estimation of the i/o power is similar to the computation of the peripheral power estimates. the power consumption per signal line is computed assuming a maximum load of 20 pf, a vo ltage swing of 3.3 v, and a switching frequency of 25 mhz or 33 mhz, which yields: p io = 20 pf (3.3 v) 2 25 mhz 10 ?3 = 5.44 mw per i/o line eqn. 16 p io = 20 pf (3.3 v) 2 33 mhz 10 ?3 = 7.19 mw per i/o line eqn. 17 multiply this number by the number of i/o signal lines used in the application design to compute the total i/o power. note: the signal loading depends on the board routing. for system s using a single ddr device, the load could be as low as 7 pf. 3.3.5 leakage power the leakage power is for all power supplies combined at a sp ecific temperature. the value is temperature dependent. the observed leakage value at room temperature is 64 mw. 3.3.6 example total power consumption using the examples in this section and assuming four peripher als and 10 i/o lines active, a total power consumption value is estimated as the following: p total (200 mhz core) = 216 + (4 2.88) + 324,2 + (10 5.44) + 64 = 670.12 mw eqn. 18 p total (266 mhz core) = 287 + (4 3.83) + 326.3 + (10 7.19) + 64 = 764.52 mw eqn. 19 3.4 reset and boot this section describes the recommendations for configuring the MSC7113 at reset and boot. 3.4.1 reset circuit hreset is a bidirectional signal and, if driven as an input, should be driven with an open coll ector or open-drain device. for an open-drain output such as hreset , take care when driving many buffers that implement input bus-hold circuitry. the bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic le vel to low. either a smaller value of pull-up or less current loading from the bus-hold driv ers overcomes this issue. to avoid exceeding the MSC7113 output current, the pull-up value should not be too small (a 1 k pull-up resistor is used in the msc711xads reference design).
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 52 3.4.2 reset configuration pins table 34 shows the MSC7113 reset configuration signals. these si gnals are sampled at the deassertion (rising edge) of poreset . for details, refer to the reset chapter of the msc711x reference manual . 3.4.3 boot after a power-on reset, the pll is bypassed and the device is directly clocked from the clkin pin. using this input clock, the system initializes using the boot loader program that resides in the internal rom. after initialization, the dsp core can enable the pll and start the device operating at a higher speed. the MSC7113 can boot from an external host through the hdi16 or download a user program through the i 2 c port. the boot operating mode is set by configuring the bm[1?0] signals sampled at the rising edge of poreset, as shown in ta b l e 3 5 . 3.4.3.1 hdi16 boot if the MSC7113 device boots from an external host th rough the hdi16, the port is configured as follows: ? operate in non-dma mode. ? operate in polled mode on the device side. ? operate in polled mode on the external host side. ? external host must write four 16-bit values at a time with the first word as the most significant and the fourth word as the least significant. when booting from a power-on reset, the hdi16 is additionally configurable as follows: ? 8- or 16-bit mode as specified by the h8bit pin. ? data strobe as specified by the hdsp and hdds pins. these pins are sampled only on the deassertion of power-on reset. during a boot from a hard reset, the configuration of these pins is unaffected. note: when the hdi16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit as for other dsp products. table 34. reset configuration signals signal description settings bm[1?0] determines boot mode. 0 boot from hdi16 port. 01 boot from i2c. 1x reserved. swte determines watchdog functionality. 0 watchdog timer disabled. 1 watchdog timer enabled. hdsp configures hdi16 strobe polarity. 0 host data strobes active low. 1 host data strobes active high. h8bit configures hdi16 operation mode. 0 hdi 16 port configured for 16-bit operation. 1 hdi16 port configured for 8-bit operation. table 35. boot mode settings bm1 bm0 boot source 0 0 external host via hdi16 with the pll disabled. 01i 2 c. 1 0 external host via the hdi16 with the pll enabled. 1 1 reserved.
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 53 3.4.3.2 i 2 c boot when the MSC7113 device is configured to boot from the i 2 c port, the boot program configures the gpio pins shared with the i 2 c pins as i 2 c pins. the i 2 c interface is configured as follows: ?i 2 c in master mode. ? eprom in slave mode. for details on the boot procedure, s ee the ?boot program? chapter of the msc711x reference manual . 3.5 ddr memory system guidelines MSC7113 devices contain a memory controlle r that provides a glueless interface to external double data rate (ddr) sdram memory modules with class 2 series stub termination logic 2. 5 v (sstl_2). there are two termination techniques, as shown in figure 36 . technique b is the most popular termination technique. figure 37 illustrates the power wattage for the resistors. typical values for the resistors are as follows: ? rs = 22 ?rt = 24 figure 36. sstl termination techniques controller address command chip selects data strobes mask vref vtt terminator v tt generator ddr bank ddr bank v tt sstl_2 sstl_2 sstl_2 rs rt rt rs controller address command chip selects data strobes mask vtt terminator island v tt generator ddr bank ddr bank sstl_2 sstl_2 sstl_2 rs rt rt rs technique a technique b
MSC7113 data sheet, rev. 11 hardware design considerations freescale semiconductor 54 3.5.1 v ref and v tt design constraints v tt and v ref are isolated power supplies at the same voltage, with v tt as a high current power source. this section outlines the voltage supply design needs and goals: ? minimize the noise on both rails. ?v tt must track variation in the v ref dc offsets. although they are isolated supplies, one possible solution is to use a single ic to generate both signals. ? both references should have minimal drift over temperature and source supply. ? it is important to minimize the noise from coupling onto v ref as follows: ? isolate v ref and shield it with a ground trace. ? use 15?20 mm track. ? use 20?30 mm clearance between other traces for isolating. ? use the outer layer route when possible. ? use distributed decoupling to localize transient currents and return path and decouple w ith an inductance less than 3 nh. ? max source/sink transient currents of up to 1.8 a for a 32-bit data bus. ? use a wide island trace on the outer layer: ? place the island at the end of the bus. ? decouple both ends of the bus. ? use distributed decoup ling across the island. ? place sstl termination resistors inside the v tt island and ensure a good, solid connection. ? place the v tt regulator as closely as possible to the termination island. ? reduce inductance and return path. ? tie current sense pin at the midpoint of the island. 3.5.2 decoupling the ddr decoupling considerations are as follows: ? ddr memory requires significantly more burst current than previous sdrams. ? in the worst case, up to 64 drivers may be switching states. ? pay special attention and decouple disc rete ics per manufacturer guidelines. ? leverage v tt island topology to minimize the number of capacitors required to supply the burst current needs of the termination rail. ? see the micron designline publication entitled decoupling capacitor calculation for a ddr memory channel ( http://download.micron.com/pdf/pubs/designline/3q00dl1-4.pdf ). figure 37. sstl power value driver receiver v ref v ddq v ss v tt rs rt
hardware design considerations MSC7113 data sheet, rev. 11 freescale semiconductor 55 3.5.3 general routing the general routing considerations for the ddr are as follows: ? all ddr signals must be routed next to a solid reference: ? for data, next to solid ground planes. ? for address/command, power planes if necessary. ? all ddr signals must be impedance controlled. this is system dependent, but typical values are 50?60 ohm. ? minimize other cross-talk opportunities. as possible, mainta in at least a four times the trace width spacing between all ddr signals to non-ddr signals. ? keep the number of vias to a minimum to eliminate additional stubs and capacitance. ? signal group routing priorities are as follows: ? ddr clocks. ? route mvtt/mvref. ? data group. ? command/address. ? minimize data bit jitter by trace matching. 3.5.4 routing clock distribution the ddr clock distribution considerations are as follows: ? ddr controller supports six clock pairs: ? 2 dimm modules. ? up to 36 discrete chips. ? for route traces as for any other differential signals: ? maintain proper difference pair spacing. ? match pair traces within 25 mm. ? match all clock traces to within 100 mm. ? keep all clocks equally loaded in the system. ? route clocks on inner critical layers. 3.5.5 data routing the ddr data routing considerations are as follows: ? route each data group (8-bits data + dqs + dm ) on the same layer. avoid switching layers within a byte group. ? take care to match trace lengths, which is extremely important. ? to make trace matching easier, let adjacent groups be routed on alternate critical layers. ? pin swap bits within a byte group to facilitate routing (discrete case). ? tight trace matching is recommended with in the ddr data group. keep each 8-b it datum and its dm signal within 25 mm of its respective strobe. ? minimize lengths across the entire ddr channel: ? between all groups maintain a delta of no more than 500 mm. ? allows greater flexibility in the design for readjustments as needed. ? ddr data group separation: ? if stack-up allows, keep ddr data groups away from the address and control nets. ? route address and control on separate critical layers. ? if resistor networks (rns) are used, attempt to k eep data and command lines in separate packages.
MSC7113 data sheet, rev. 11 ordering information freescale semiconductor 56 3.6 connectivity guidelines this section summarizes the connections and special conditions , such as pull-up or pull-down resistors, for the MSC7113 device. following are guidelines for signal groups and configuration settings: ? clock and reset signals . ? swte is used to configure the MSC7113 device and is sampled on the deassertion of poreset , so it should be tied to v ddc or gnd either directly or through pull-up or pull-down resistors until poreset is deasserted. after poreset , this signal can be left floating. ? bm[0?1] configure the MSC7113 device and are sampled until poreset is deasserted, so they should be tied to v ddio or gnd either directly or through pull-up or pull-down resistors. ? hreset should be pulled up. ? interrupt signals . when used, irq pins must be pulled up. ? hdi16 signals . ? when they are configured for open-drain, the hreq /hreq or htrq/ htrq signals require a pull-up resistor. however, these pins are also sampled at power-on reset to determine the hdi16 boot mode and may need to be pulled down. when these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with the hreset signal as the enable. ? when the device boots through the hdi16, the hdds, hdsp and h8bit pins should be pulled up or down, depending on the required boot mode settings. ? ethernet mac/tdm2 signals . the mdio signal requires an external pull-up resistor. ? i 2 c signals . the scl and sda signals, when programmed for i 2 c, requires an external pull-up resistor. ? general-purpose i/o (gpio) signals . an unused gpio pin can be disconnected. after boot, program it as an output pin. ? other signals. ?the test0 pin must be connected to ground. ?the tpsel pin should be pulled up to enable debug access via the eonce port and pulled down for boundary scan. ? pins labelled no connect (nc) must not be connected. ? when a 16-pin double data rate (ddr) interface is used, th e 16 unused data pins should be no connects (floating) if the used lines are terminated. ? do not connect dbreq to done (as you would for the msc8101 device). connect done to one of the evnt pins, and dbreq to hrrq . 4 ordering information consult a freescale semiconductor sales office or authorized dist ributor to determine product av ailability and place an order. part supply voltage package type pin count core frequency (mhz) solder spheres order number MSC7113 (mask 1l44x 1.2 v core 2.5 v mem. 3.3 v i/o molded array process-ball grid array (map-bga) 400 200 lead-free MSC7113vm800 lead-bearing MSC7113vf800 MSC7113 (mask 1m88b) 1.2 v core 2.5 v mem 3.3 v i/o molded array process-ball grid array (map-bga) 400 266 lead-free MSC7113vm1000 lead-bearing MSC7113vf1000
package information MSC7113 data sheet, rev. 11 freescale semiconductor 57 5 package information 6 product documentation ? msc711x reference manual (msc711xrm). includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. ? application notes . cover various programming topics related to the starcore dsp core and the MSC7113 device. ? sc140/sc1400 dsp core reference manual . covers the sc140 and sc1400 core architecture, control registers, clock registers, program control, and instruction set. figure 38. MSC7113 mechanical information, 400-pin map-bga package case 1568-01 notes: 1. all dimensions in millimeters. 2. dimensioning and tolerancing per asme y14.5m?1994. 3. maximum solder ball diameter measured parallel to datum a . 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement sha ll exclude any effect of mark on top surface of package.
MSC7113 data sheet, rev. 11 revision history freescale semiconductor 58 7 revision history table 36 provides a revision history for this data sheet. table 36. document revision history revision date description 0 apr 2004 ? initial public release. 1 may 2004 ? added ordering information and new package options. 2 aug. 2004 ? updated clock parameter values. ? updated ddr timing specifications. ? updated i 2 c timing specifications. 3 sep. 2004 ? updated figures 1-2 and 1-2 to correct hdsp and dbreq. ? corrected ee0 port reference. ? updated ball location for hdsp. 4 jan. 2005 ? added signal ha3. ? updated absolute maximum ratings, ddr dram capacitance specifications, clock parameters, reset timing, and tdm timing. ? added note for timing reference for i 2 c interface. ? expanded gpio timing information. ? corrected pin t20 and k20 signal designation. ? corrected signal names to gpao15 and irq2 . ? expanded design guidelines in chapter 4. 5 mar. 2005 ? updated features list. ? updated power specifications. ? changed clkin frequency range. ? added clock configuration information. ? updated jtag timings. 6 apr. 2005 ? added recommended power supply ratings and updated equations to estimate power consumption. 7 oct. 2005 ? updated core and total power consumption examples. 8 dec. 2005 ? added information about signals gpioa16, gpioa 17, gpioa27, gpioa28, and gpioa29 to signal description and pinout location lists. 9 nov. 2006 ? updated reference manual reference to msc711x reference manual. ? updated arrows in host dma writing timing figure. ? updated boot overview. 10 aug. 2007 ? updated to new data sheet format. reorganized and renumbered sections, figures, and tables. ? added a note to clarify the definition of tck timing 700 in new table 31 . ? the power-up and power-down sequences have been expanded to five possible design scenarios/cases. these cases replace the previously recommended power-up/power-down sequence recommendations. the section has been clarified by adding subsection headings. 11 apr 2008 ? change the pll filter resistor from 20 to 2 in section 3.2.5 .
revision history MSC7113 data sheet, rev. 11 freescale semiconductor 59
document number: MSC7113 rev. 11 4/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-m eguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale?, the freescale logo, codewarrior, fieldbist, and starcore are trademarks of freescale semiconductor, inc. ieee, 802.3, 802.3u, 802.3x, and 802.3ac are trademarks of the institute of electrical and electronics engineers, inc. (ieee). all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004, 2008. all rights reserved.

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